1. Field of the Invention
The invention relates to a circuit configuration for digital bit-serial signal processing.
Bit-serial processing of time and amplitude-discrete data is intrinsically superior in various aspects to bit-parallel processing. Only a few connections and leads are necessary for bit-serial processing, and the total expenditure for data processing circuitry is also low. The expenditure increases with the word length of the data to a much lesser extent than is the case with bit-parallel processing. The data flow is also markedly higher. Such characteristics are highly advantageous above all for realizations in very large scale integration technology, since they make very compact and effective topologies possible.
However, in bit-serial processing, a very high expenditure for circuitry is necessary both for controlling and in particular for equalizing the transit time for various data paths and for processing the algebraic sign. A further factor is a long overall processing time. Above all, in bit-serial configurations that have feedbacks, such as recursive digital filters in general and wave digital filters in particular, or those that operate by time multiplexing, the circuitry expenditure and processing times are multiplied. As a result, bit-parallel processing has thus far predominantly been preferred over bit-serial processing.